Field Programmable Gate Array (FPGA) Based Collision Avoidance Using Acceleration Velocity Obstacles

Roopak Dubey*    Neeraj Pradhan*    K. Madhava Krishna    Shubhajit Roy Chowdhury   

IIIT Hyderabad, India   

This paper presents a Field Programmable Gate Array (FPGA) based implementation of Acceleration Velocity Obstacle based Collision Avoidance for an omni-directional robot with acceleration constraint. Specifically a parallel architecture for collision avoidance is proposed that portrays the advantages of FPGA implementation over the sequential implementation for same processor or clock speed. FPGA based robotics is seen to gain popularity due to low cost, portability, seamless interface to hardware and most importantly due to inherent parallelism enshrined in various robotic algorithms. FPGA realization of the algorithm in a simulation test bed vindicates its efficacy and comparison with sequential implementation is also highlighted. The paper proposes three different architectures for the implementation of the proposed algorithm viz. sequential architecture; a resource constrained pipelined architecture and a hybrid pipeline parallel architecture. The performances of those three architectures have been evaluated.